Symbolic trajectory evaluation for word-level verification: theory and implementation
Artikel i vetenskaplig tidskrift, 2017

Symbolic trajectory evaluation (STE) is a model checking technique that has been successfully used to verify many industrial designs. Existing implementations of STE reason at the level of bits, allowing signals in a circuit to take values from a lattice comprised of three elements: 0, 1, and X. This limits the amount of abstraction that can be achieved, and presents limitations to scaling STE to even larger designs. The main contribution of this paper is to show how much more abstract lattices can be derived automatically from register-transfer level descriptions, and how a model checker for the general theory of STE instantiated with such abstract lattices can be implemented in practice. We discuss several implementation issues, including how word-level circuits can be symbolically simulated using a new encoding for words that allows representing X values of sub-words succinctly. This gives us the first practical word-level STE engine, called STEWord. Experiments on a set of designs similar to those used in industry show that STEWord scales better than bit-level STE, as well as word-level bounded model checking.

Symbolic trajectory evaluation

Word-level verification

X-based abstraction

SMT solving


S. Chakraborty

Indian Institute of Technology Bombay

Z. Khasidashvili

Intel Development Center, Israel

Carl-Johan Seger

Funktionell programmering

R. Gajavelly

Indian Institute of Technology Bombay

T. Haldankar

Indian Institute of Technology Bombay

D. Chhatani

Indian Institute of Technology Bombay

R. Mistry

Indian Institute of Technology Bombay

Formal Methods in System Design

0925-9856 (ISSN) 1572-8102 (eISSN)

Vol. 50 2-3 317-352



Inbäddad systemteknik




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