Micro-architectural power estimation and optimization
Paper i proceeding, 2009

Today power optimization is an important field of research due to the increasing need for less power consumption, dramatic decrease of circuit's MTBF on high temperature and cooling difficulties. It is investigated that only 30% improvement in battery performance will be obtained in five years [1]. This paper is an overview on Power estimation and optimization researches and the overall flow of presenting the information is based on the reference [17]. We review the architectural template and the methods to provide model for power consumption of different types of components. Some common optimization techniques including clock-gating, exploiting the common case of the design and managing voltage are being reviewed.

Författare

Babak Hidaji

Chalmers, Data- och informationsteknik, Datorteknik

Mohamad Reza Andalibizadeh

Chalmers, Data- och informationsteknik

Salar Alipour

Chalmers, Data- och informationsteknik, Datorteknik

2009 IEEE International Conference on Electro/Information Technology, EIT 2009; Windsor, ON; Canada; 7 June 2009 through 9 June 2009

446-450

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1109/EIT.2009.5189658

ISBN

978-142443355-1