A fault tolerant method for residue arithmetic circuits
Paper i proceeding, 2009

As a result of shrinking device dimensions, the occurrence of transient errors is increasing. This causes system reliability to be reduced. Thus, fault-tolerant methods are becoming increasingly important, particularly in safety-critical applications. In this paper a novel fault-tolerant method is proposed through combining time redundancy with information redundancy to reduce hardware complexity. Residue codes are selected as the source of information redundancy and the proposed technique is compared with some well-known fault tolerant schemes considering required hardware and delay. This method can be applied to various types of arithmetic circuits. Simulations results of a multiplier circuit showes that by using Quadruple Residue Redundancy in comparison with a simple Residue Redundancy when multiplying two 64-bit numbers, number of gates can be reduced to 90% by exposing only 9% extra delay. Therefore, this technique can effectively reduce hardware complexity and consequently leads to large savings on the ALU as a whole, while introducing only a reasonable delay.

Residue code

Time redundancy

Hardware complexity

Fault tolerance

Författare

Rana Forsati

Islamic Azad University, Karaj Branch

Karim Faez

Amirkabir University of Technology

Farnaz Moradi

Chalmers, Data- och informationsteknik, Nätverk och system

Afsaneh Rahbar

Islamic Azad University

2009 International Conference on Information Management and Engineering, ICIME 2009; Kuala Lumpur; Malaysia; 3 April 2009 through 5 April 2009

59-63

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1109/ICIME.2009.111

ISBN

978-076953595-1