A fault tolerant method for residue arithmetic circuits

Paper i proceeding, 2009

As a result of shrinking device dimensions, the occurrence of transient errors is increasing. This causes system reliability to be reduced. Thus, fault-tolerant methods are becoming increasingly important, particularly in safety-critical applications. In this paper a novel fault-tolerant method is proposed through combining time redundancy with information redundancy to reduce hardware complexity. Residue codes are selected as the source of information redundancy and the proposed technique is compared with some well-known fault tolerant schemes considering required hardware and delay. This method can be applied to various types of arithmetic circuits. Simulations results of a multiplier circuit showes that by using Quadruple Residue Redundancy in comparison with a simple Residue Redundancy when multiplying two 64-bit numbers, number of gates can be reduced to 90% by exposing only 9% extra delay. Therefore, this technique can effectively reduce hardware complexity and consequently leads to large savings on the ALU as a whole, while introducing only a reasonable delay.