Code density concerns for new architectures
Paper i proceeding, 2009

Reducing a program's instruction count can improve cache behavior and bandwidth utilization, lower power consumption, and increase overall performance. Nonetheless, code density is an often overlooked feature in studying processor architectures. We hand-optimize an assembly language embedded benchmark for size on 21 different instruction set architectures, finding up to a factor of three difference in code sizes from ISA alone. We find that the architectural features that contribute most heavily to code density are instruction length, number of registers, availability of a zero register, bit-width, hardware divide units, number of instruction operands, and the availability of unaligned loads and stores. We extend our results to investigate operating system, compiler, and system library effects on code density. We find that the executable starting address, executable format, and system call interface all affect program size. While ISA effects are important, the efficiency of the entire system stack must be taken into account when developing a new dense instruction set architecture.


Vincent M. Weaver

Cornell University

Sally A McKee

Chalmers, Data- och informationsteknik, Datorteknik

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

10636404 (ISSN)

459-464 5413117
978-142445028-2 (ISBN)


Data- och informationsvetenskap





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