Superconductor Digital Signal Processor
Doktorsavhandling, 2007

Superconductor digital technology based on Rapid Single Flux Quantum logic (RSFQ) offers more than 50 times gain in speed and more than 100 reduction in power consumption over mainstream CMOS devices. However, the necessity of cooling down to 4 K and modest degree of integration density currently available mean that employing RSFQ is reasonable only for the tasks that are impossible or ineffective to implement in CMOS technology. One of the promising applications of the RSFQ technology is Digital Signal Processing (DSP) for telecommunications. Interference cancellation is a bottleneck for all existing systems in terms of the performance gain that is theoretically possible and technically realizable using conventional technology. The crucial factor is computational complexity required to handle multiple access interference. The general approach is to compute the interference using available data about propagation channels and then either remove it from received signal or use to predistort the transmitted signal. Computation of the interference matrix can easily fall into 100 Gops range, furthermore, the most e±cient algorithms are based on successive iterations. This requires not only high overall performance of the DSP but also high actual clock rate. This thesis reports a proposed architecture of an RSFQ Successive Interference Canceller and a design of an RSFQ Digital Signal Processor based on hybrid RSFQ-CMOS memory suitable for a general matrix on matrix multiplication algorithm. The processor consists of an RSFQ Multiply-Accumulate Unit, memory caches and a synchronization block, partitioned into multiple chips, and a large CMOS memory. The complexity of the RSFQ DSP is 10x10 multiplication, rounding to 14 bits, 18 bits accumulator length and 3.7 Kb memory cache. In order to implement the RSFQ DSP, we have developed approach to simulate and describe the RSFQ circuits using VHDL. The maximum simulated clock frequency is equal to 24 GHz for Hypres 4.5 kA/cm2 process and optimum communication bandwidth with CMOS memory is 2 Gbps. Components of the processor such as 4x4 two's complement and 5x5 parallel multipliers, 4x5, 20x5 and 4x15 parallel shift registers, a 5-bit serial adder have been designed and experimentally tested. The simplified version of the RSFQ DSP consisting of a 4x4 MAC with rounding to 5 bits and 17x6 memory caches has been designed for Hypres 4.5 kA/cm2 process and fabricated.

Rapid Single Flux Quantum logic (RSFQ)

multiuser detector


Multiply-Accumulate Unit

Successive Interference Canceller

10.15 Kollektorn, Kemivagen 9, Chalmers
Opponent: Dr. Steve Kaplan, Hypres Inc., USA


Irina Kataeva

Chalmers, Mikroteknologi och nanovetenskap (MC2), Kvantkomponentfysik

Time-Delay Optimization of RSFQ Cells

IEEE Transactions on Applied Superconductivity,; Vol. 15(2005)p. 328-331

Artikel i vetenskaplig tidskrift

RSFQ Parallel Multiplier

Applied Superconductivity 2003, EUCAS sorrento Italy, conference series number 181,; (2003)

Konferensbidrag (offentliggjort, men ej förlagsutgivet)

RSFQ Digital Signal Processor for Interference Cancellation

Applied superconductivity conference,; (2004)

Paper i proceeding

Scalable Matrix Multiplication with Hybrid CMOS-RSFQ Digital Signal Processor

oral presentation Applied Superconductivity Conference (ASC) Sept 2006, Seattle, will be published in IEEE Transactions on Applied Superconductivity June 2007,; Vol. June(2007)

Paper i proceeding

New Design of a RSFQ Parallel Multiply-Accumulate Unit

Superconducting Science and technology,; Vol. 19(2006)p. S381-S386

Artikel i vetenskaplig tidskrift


Annan elektroteknik och elektronik



Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 2602

Technical report MC2 - Department of Microtechnology and Nanoscience, Chalmers University of Technology: MC2-94

10.15 Kollektorn, Kemivagen 9, Chalmers

Opponent: Dr. Steve Kaplan, Hypres Inc., USA