Accurate Leakage-Conscious Architecture-Level Power Estimation for SRAM-based Memory Structures
Doktorsavhandling, 2007

Following Moore’s Law, technology scaling will continue providing integration capacity of billions of transistors for IC industry. As transistors keep shrinking in size, leakage power dissipation dramatically increases and gradually becomes a first-class design constraint. To provide higher performance at lower power and energy for micro-architectures, on-chip caches are growing in size and thus become a major contributor to the total leakage power dissipation in next-generation processors. In these circumstances, accurate leakage power estimation obviously is needed to allow designers to strike a balance between dynamic power and leakage power, and between total power and delay in on-chip caches. This dissertation presents a modular, hybrid power modeling methodology capable of capturing accurately both dynamic and leakage power mechanisms for on-chip caches and for SRAM arrays. The methodology successfully combines the most valuable advantage of circuit-level power estimation – high accuracy – with the flexibility of higher-level power estimation while allowing for short component characterization and estimation time. The methodology offers high-level parameterizable, but still accurate power dissipation estimation models that consist of analytical equations for dynamic power and pre-characterized leakage power values stored in tables. In addition, a modeling methodology to capture the dependence of leakage power on temperature variation, on supply-voltage scaling, and on the selection of process corners has also been presented. This methodology provides an essential extension to the proposed power models.

SRAM Power Modeling

Deep Submicron

Power-Performance Estimation Tool

VLSI

Power Estimation

DSP Architecture

CMOS

Cache Power Modeling

HC1, Hörsalsvägen, Chalmers
Opponent: Prof. David Brooks, Division of Engineering and Applied Science, Harvard University, Cambridge, Massachusetts, USA

Författare

Minh Quang Do

Chalmers, Data- och informationsteknik, Datorteknik

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration

International Symposium on Quality Electronic Design (ISQED),; (2006)

Paper i proceeding

Table-Based Total Power Consumption Estimation of Memory Arrays for Architects

Lecture Notes in Computer Science (LNCS) , Springer Verlag,; Vol. 3254(2004)p. 869-878

Paper i proceeding

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

8th International Symposium on Quality Electronic Design (ISQED’07),; (2007)p. 185 - 191

Paper i proceeding

Ämneskategorier

Annan elektroteknik och elektronik

ISBN

978-91-7291-968-6

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 2649

HC1, Hörsalsvägen, Chalmers

Opponent: Prof. David Brooks, Division of Engineering and Applied Science, Harvard University, Cambridge, Massachusetts, USA