Improving Execution Efficiency by Targeting Redundancy and Parallelism
Licentiatavhandling, 2007

trivial computation

redundancy

performance

thread-level parallelism

thread-level speculation

chip-multiprocessors

looptrip count

energy-efficiency

instruction reuse

control speculation.

Room VK, Sven Hultins gata 6, Department of Civil and Environmental Engineering, Chalmers University of Technology
Opponent: Marcelo Cintra, School of Informatics, University of Edinburgh, UK

Författare

Mafijul Islam

Chalmers, Data- och informationsteknik, Datorteknik

Loop-Level Speculative Parallelism in Embedded Applications.

2007 International Conference on Parallel Processing,; (2007)

Paper i proceeding

Energy and Performance Tradeoffs between Instruction Reuse and Trivial Computations for Embedded Applications

IEEE International Symposium on Embedded Computer Systems,; (2007)

Paper i proceeding

Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications

19th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007),; (2007)

Paper i proceeding

Ämneskategorier

Datorteknik

Technical report L - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University: 43L

Room VK, Sven Hultins gata 6, Department of Civil and Environmental Engineering, Chalmers University of Technology

Opponent: Marcelo Cintra, School of Informatics, University of Edinburgh, UK