A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI
Paper i proceeding, 2018

We present a low-density parity check (LDPC) decoder using the adaptive degeneration (AD) algorithm with a (3600, 3000) LDPC code, integrated in 1.85 mm^2 in 28 nm FD-SOI. With early termination and variable latency decoding, this decoder achieves an optimal energy efficiency of 0.16 pJ/bit and information throughput of 13.6 Gbps with a core supply voltage of 0.4 V. At a core supply voltage of 1.0 V, it achieves 0.58 pJ/bit energy efficiency and 181 Gbps throughput. With constant latency equal to the maximum number of iterations, it achieves optimal energy efficiency of 0.52 pJ/bit and information throughput of 7.2 Gbps at a supply voltage of 0.55 V, and 1.9 pJ/bit energy and 24 Gbps throughput at 1.0 V. The net coding gain at a bit error rate of 10^(−12) is 8.7 dB.


Kevin Cushon

Chalmers, Data- och informationsteknik, Datorteknik

Per Larsson-Edefors

Chalmers, Data- och informationsteknik, Datorteknik

Peter Andrekson

Chalmers, Mikroteknologi och nanovetenskap, Fotonik

Proceedings of ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference

9781538654040 (ISBN)

44th European Solid-State Circuits Conference (ESSCIRC)
Dresden, Germany,

Energieffektiv optisk fiberkommunikation

Knut och Alice Wallenbergs Stiftelse (KAW2013.0021), 2014-07-01 -- 2019-06-30.


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