Building Verified Hardware and Verified Stacks in HOL
Licentiatavhandling, 2019

This thesis explores building provably correct software and hardware inside the HOL4 interactive theorem prover. Interactive theorem provers such as HOL4 are proof environments where manual (human) and automated (machine) proofs can be composed in logically safe ways, and all proof steps (be it manual or automated) are mechanically checked.

We are in particular interested in systems consisting of both software and hardware. Such systems are of relevance when building so called verified stacks. A verified stack is a computer system accompanied by a correctness theorem ensuring the correctness of its running software down to the computer system's hardware implementation.

Our foremost contribution to hardware development in HOL4 is a proof-producing tool for extracting hardware circuits proved correct inside HOL4 to the hardware description language Verilog. Verilog is one of the low-level description languages modern synthesis tools take as input. By targeting Verilog, we can close the gap between the mathematical models of proved-correct circuits inside our prover and the input to the synthesis tools that will ultimately be used in the creation of concrete hardware, e.g., FPGA artifacts, out of our hardware descriptions.

Our contribution to the tradition of building verified stacks is as follows. We have used our Verilog translator tool in the construction of a verified proof-of-concept processor that we have extracted and synthesized for an FPGA board. Building upon this work, we have used the processor as the hardware basis for verified stacks based on CakeML programs, including a stack for compiling CakeML programs and a stack for checking proofs. To be able to construct such stacks, we adapted and extended the verified CakeML compiler and its development methodology to support targeting the new processor we have constructed. The CakeML compiler previously only supported compilation to x86, ARM and other architectures without a verified implementation.

ED, EDIT building, Hörsalsvägen 11, Chalmers University of Technology
Opponent: David J. Greaves, University of Cambridge, United Kingdom

Författare

Andreas Lööw

Chalmers, Data- och informationsteknik, Formella metoder

Andreas Lööw, Ramana Kumar, Yong Kiam Tan, Magnus O. Myreen, Michael Norrish, Oskar Abrahamsson, Anthony Fox, Verified Compilation on a Verified Processor

Andreas Lööw, Magnus O. Myreen, A Proof-Producing Translator for Verilog Development in HOL

Ämneskategorier

Datavetenskap (datalogi)

Utgivare

Chalmers tekniska högskola

ED, EDIT building, Hörsalsvägen 11, Chalmers University of Technology

Opponent: David J. Greaves, University of Cambridge, United Kingdom

Mer information

Senast uppdaterat

2019-05-10