Improvement of AM-PM in a 33-GHz CMOS SOI Power Amplifier Using pMOS Neutralization
Artikel i vetenskaplig tidskrift, 2019
This letter presents two highly efficient two-stage power amplifiers (PAs) for 5G applications, implemented in a 22-nm slilicon on insulator (SOI) CMOS technology. High efficiency is achieved by carefully designing the power cells and optimizing the layout. Capacitive neutralization is used to improve the stability and the gain. Both PAs are similar except for the use of nMOS neutralization capacitors in the first one. In the second PA, we propose the use of pMOS capacitors instead to enhance significantly both stability and AM-PM linearity at the same time. For both PAs, the saturated output power is 12.7 dBm andP1 dB is 11.9 dBm from a 0.9-V supply at 33 GHz with a power-added efficiency (PAE) at P1 dB of more than 36%. The PAE at Psat is 38% and 40% for the PA with nMOS and pMOS neutralizations, respectively. The AM-PM up to P3 dB for the PA with nMOS neutralization is 7, and for the one with pMOS neutralization, it is less than 1.3 thanks to the proposed technique.
power amplifier (PA)
power-added efficiency (PAE)