Verified Compilation on a Verified Processor
Paper i proceeding, 2019

Developing technology for building verified stacks, i.e., computer systems with comprehensive proofs of correctness, is one way the science of programming languages furthers the computing discipline. While there have been successful projects verifying complex, realistic system components, including compilers (software) and processors (hardware), to date these verification efforts have not been compatible to the point of enabling a single end-to-end correctness theorem about running a verified compiler on a verified processor. In this paper we show how to extend the trustworthy development methodology of the CakeML project, including its verified compiler, with a connection to verified hardware. Our hardware target is Silver, a verified proof-of-concept processor that we introduce here. The result is an approach to producing verified stacks that scales to proving correctness, at the hardware level, of the execution of realistic software including compilers and proof checkers. Alongside our hardware-level theorems, we demonstrate feasibility by hosting and running our verified artefacts on an FPGA board.

hardware verification

verified stack

program verification

compiler verification

Författare

Andreas Lööw

Göteborgs universitet

Ramana Kumar

DeepMind

Yong Kiam Tan

Carnegie Mellon University (CMU)

Magnus O. Myreen

Göteborgs universitet

Michael Norrish

Australian National University

CSIRO

Oskar Abrahamsson

Chalmers, Data- och informationsteknik, Formella metoder

Anthony Fox

Arm Ltd

PROCEEDINGS OF THE 40TH ACM SIGPLAN CONFERENCE ON PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION (PLDI '19)

1041-1053

40th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI) part of ACM's Federated Computing Research Conference (FCRC)
Phoenix, AZ, USA,

Ämneskategorier

Data- och informationsvetenskap

Programvaruteknik

DOI

10.1145/3314221.3314622

Mer information

Senast uppdaterat

2020-06-30