Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder
Artikel i vetenskaplig tidskrift, 2021

Variable-rate transceivers, which adapt to the conditions, will be central to energy-efficient communication. However, fiber-optic communication systems with high bit-rate requirements make design of flexible transceivers challenging, since additional circuits needed to orchestrate the flexibility will increase area and degrade speed. We propose a variable-rate VLSI architecture of a forward error correction (FEC) decoder based on hard-decision product codes. Variable shortening of component codes provides a mechanism by which code rate can be varied, the number of iterations offers a knob to control the coding gain, while a key-equation solver module that can swap between error-locator polynomial coefficients provides a means to change error correction capability. Our evaluations based on 28-nm netlists show that a variable-rate decoder implementation can offer a net coding gain (NCG) range of 9.96-10.38 dB at a post-FEC bit-error rate of 10^-15. The decoder achieves throughputs in excess of 400 Gb/s, latencies below 53 ns, and energy efficiencies of 1.14 pJ/bit or less. While the area of the variable-rate decoder is 31% larger than a decoder with a fixed rate, the power dissipation is a mere 5% higher. The variable error correction capability feature increases the NCG range further, to above 10.5 dB, but at a significant area cost.

Optical communication

variable rate transceivers

high throughput

energy efficiency

forward error correction

product codes

very large scale integration (VLSI)


Vikram Jain

KU Leuven

Christoffer Fougstedt

Chalmers, Data- och informationsteknik, Datorteknik

Per Larsson-Edefors

Chalmers, Data- och informationsteknik, Datorteknik

IEEE Transactions on Circuits and Systems I: Regular Papers

1549-8328 (ISSN)

Vol. 68 1 25-34 9252866


Informations- och kommunikationsteknik


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