An Investigation of the Fault Sensitivity of Four Benchmark Workloads
Paper i proceeding, 2012

This paper presents an experimental study of the fault sensitivity of four programs included in the MiBench test suit. We investigate their fault sensitivity with respect to hardware faults that manifest as single bit flips in main memory locations and instruction set architecture registers. To this end, we have conducted extensive fault injection experiments with two versions of each program, one basic version and one where the program is equipped with software- implemented hardware fault tolerance (SIHFT) through triple time redundant execution, majority voting and forward recovery (TTR-FR). The results show that TTR-FR achieves an error coverage between 94.6% and 99.2%, while the non- fault-tolerant versions achieve an error coverage between 55.8% and 81.1%. To gain understanding of the origin of the non-covered faults, we provide statistics on the fault sensitivity of different source code blocks, physical fault locations (instruction set architecture registers and main memory words) and different categories of machine instructions.

failure mode distributions

microprocessor faults

fault injection

fault sensitivity.

software-implemented hardware fault tolerance


Behrooz Sangchoolie

Chalmers, Data- och informationsteknik, Datorteknik

Fatemeh Ayatolahi

Chalmers, Data- och informationsteknik, Datorteknik

Johan Karlsson

Chalmers, Data- och informationsteknik, Datorteknik

Lecture Notes in Informatics

1617-5468 (ISSN)

Vol. 208 468-479
978-3-88579-602-2 (ISBN)


Informations- och kommunikationsteknik






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