Lutsig: A Verified Verilog Compiler for Verified Circuit Development
Paper i proceeding, 2021

We report on a new verified Verilog compiler called Lutsig. Lutsig currently targets (a class of) FPGAs and is capable of producing technology mapped netlists for FPGAs. We have connected Lutsig to existing Verilog development tools, and in this paper we show how Lutsig, as a consequence of this connection, fits into a hardware development methodology for verified circuits in the HOL4 theorem prover. One important step in the methodology is transporting properties proved at the behavioral Verilog level down to technology mapped netlists, and Lutsig is the component in the methodology that enables such transportation.

Författare

Andreas Lööw

Chalmers, Data- och informationsteknik, Formella metoder

Proceedings of the 10th ACM SIGPLAN International Conference on Certified Programs and Proofs

International Conference on Certified Programs and Proofs
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Ämneskategorier

Data- och informationsvetenskap

DOI

10.1145/3437992.3439916

Mer information

Skapat

2021-08-13