Low-Temperature (Cryogenic) Transport in Gate-All-Around (GAA) Silicon Nanowire Field-Effect Transistor

Paper i proceeding, 2024

This work explores the temperature dependency of the performance of an ultra-thin silicon nanowire (SiNW) gate-all-around field-effect transistor (GAA-FET). The nanowire is assumed coaxially aligned with an ideal cylindrical gate-all-around device. The nanowire is [110] axially aligned with a diameter of 1.3 nm. Electron transport is modeled using Ensemble Monte Carlo (EMC) simulations coupled self-consistently with an electrostatic solver that solves Gauss Law in integral form. Electron scattering mechanisms include bulk silicon longitudinal acoustic and optical phonons. A wide range of temperatures is considered - from 4 K to 150 K to understand the effects of temperature on device performance under both steady-state and device switching conditions. The device is seen to work appropriately for the temperature range considered. The differences in device currents for different temperatures is attributed to the differences in the electron scattering rates for the various temperatures.