Low-Power Complex Multiplier Pin Assignment Based on Spatial and Temporal Signal Properties

Paper i proceeding, 2025

Fixed-point integer multipliers are power-intensive components that are integral to many systems in computing and digital signal processing. Operating on complex fixed-point numbers, the complex multiplier is critical to a wide range of applications including communication systems. Since channel properties drift over time, communication systems require adaptive processing blocks which have to be designed for the worst-case scenario. This raises the question of how we can take advantage of performance variations of a system to reduce power dissipation. We describe how knowledge on variations in both dynamic range (the spatial dimension) and switching frequency (the temporal dimension) can be used to assign pins of complex multipliers in order to minimize power dissipation. Using netlist synthesis based on the predictive 7-nm ASAP7 cell library, we find that, for instance, if one of two 12-bit input signals of the complex multiplier has a 2-bit reduced dynamic range and a 50% reduced switching frequency, we decrease the energy per operation by 20% by selecting the optimal pin assignment.