The Synchronization Power of Coalesced Memory Accesses
Multicore processor architectures have established themselves as the new generation of processor architectures. As part of the one core to many cores evolution, memory access mechanisms have advanced rapidly. Several new memory access mechanisms have been implemented in many modern commodity multicore processors. Memory access mechanisms, by devising how processors access the shared memory, directly in uence the synchronization capability of the multicore processor. Therefore, it is crucial to investigate the synchronization power of the new memory access mechanisms.
This paper investigates the synchronization power of coalesced memory accesses, the new memory access mechanisms introduced in recent large multicore architectures like the CUDA graphics processors. We rst design three memory access models to capture the fundamental features of the new memory access mechanisms. Subsequently, we prove the exact synchronization power of these models in terms of their consensus numbers. These tight results show that the coalesced memory access models can support strong synchronization capability to the threads of multicore processors, without the need of synchronization primitives other than reads and writes. In the case of the contemporary CUDA processors, our results imply that the coalesced memory access models have consensus numbers up to thirty two.
memory access models