Meeting Challenges in Computer Architecture (MECCA)

Research Project, 2014 – 2019

Computer technology has doubled computational performance every 24 months, over the past several decades. This performance growth rate has been an enabler for the dramatic innovation in information technology that now embraces our society. Before 2004, application developers could exploit this performance growth rate with no effort. However, since 2004 power consumption of computer chips exceeded the allowable limits and from that point and onwards, parallel computer architectures became the norm. Currently, parallelism is completely exposed to application developers and managing it is difficult and time-consuming. This has a serious impact on software productivity that may stall progress in information technology.Technology forecasts predict that by 2020 there will be hundreds of processors on a computer chip. Apart from managing parallelism, keeping power consumption within allowable limits will remain a key roadblock for maintaining historical performance growth rates. Power efficiency must increase by an order of magnitude in the next ten years to not limit the growth rate. Finally, computer chips are also key components in embedded controllers, where stringent timing responses are mandatory. Delivering predictable and tight response times using parallel architectures is a challenging and unsolved problem.MECCA takes a novel, interdisciplinary and unconventional approach to address three important challenges facing computer architecture the three Ps: Parallelism, Power, and Predictability in a unified framework. Unlike earlier, predominantly disciplinary approaches, MECCA bridges layers in computing systems from the programming language/model, to the compiler, to the run-time/OS, down to the architecture layer. This opens up for exchanging information across layers to manage parallelism and architectural resources in a transparent way to application developers to meet challenging performance, power, and predictability requirements for future computers.

Participants

Funding

Publications

Adaptive Microarchitectural Optimizations to Improve Performance and Security of Multi-Core Architectures

Techniques to Improve Energy Efficiency on Heterogeneous Multiprocessors under Timing and Quality Constraints

Bounding the execution time of parallel applications on unrelated multiprocessors

Reliability Analysis of Compressed CNNs

Multi-LSTM Acceleration and CNN Fault Tolerance

Scheduling techniques to improve the worst-case execution time of real-time parallel applications on heterogeneous platforms

Federated Scheduling of Sporadic DAGs on Unrelated Multiprocessors

Adaptive Resource Management Techniques for High Performance Multi-Core Architectures

High Performance Hybrid Memory Systems with 3D-stacked DRAM

DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors

Techniques to Save Energy in Heterogeneous Multicore Architectures under QoS Constraints

QoS-driven coordinated management of resources to save energy in multi-core systems

Energy-efficient Runtime Management of Heterogeneous Multicores using Online Projection

Runtime Management of Multiprocessor Systems for Fault Tolerance, Energy Efficiency and Load Balancing

QoS Driven Coordinated Management of Resources to Save Energy in Multi-Core Systems

Techniques to Tighten the Upper Bound on the ExecutionTime of Task-based Parallel Applications

Elastic Places: An Adaptive Resource Manager for Scalable and Portable Performance

Runtime-Assisted Global Cache Management for Task-based Parallel Programs

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