Detection and removal of traps at the SiO2/SiC interface

Doctoral thesis, 2004

The interface between silicon dioxide (SiO2) and silicon carbide (SiC) is at the heart of the SiC metal-oxide-semiconductor field-effect (MOSFET) transistor. The technology to produce a high quality SiO2/SiC interface does not exist today, hampering further development of the SiC MOSFET. This work focuses on studying electron and hole traps at the SiO2/SiC interface and reports on our progress in reducing their numbers. We examine the SiO2/SiC interface traps by studying metal-oxide-semiconductor (MOS) capacitors made in 4H-SiC and 6H-SiC. The measurement techniques used include thermally stimulated current (TSC), capacitance-voltage, constant-capacitance deep level transient spectroscopy (CCDLTS), along with transmission electron microscopy (TEM). Both the TSC and CCDLTS methods give information about majority carrier emission from interface traps close to the semiconductor majority carrier band-edge, and they show the interface traps from an alternativ perspective, compared to traditional C-V measurements. Using TSC, we compared the native SiO2/SiC interface, i.e. the one formed using wet or dry thermal oxidation in quartz environment, on both Si-face and (1120)-face n-type 4H-SiC material and we found them to be similar. In two other experiments we compared the native SiO2/SiC interface made on Si-face 4H-SiC, and 6H-SiC. Positron annihilation spectroscopy showed that there are open-volume defects at these interfaces. TEM and nanochemical analysis demonstrated that there are no extended carbon clusters at the SiO2/SiC interface in samples which were annealed at 950°C in pyrogenic steam for 3 h. By incorporating impurities into the oxide during thermal oxidation of off-axis Si-face 4H-SiC we found that it is possible to reduce the interface state density near the SiC conduction band-edge by two orders of magnitude. The impurity source used was sintered alumina and presently we do not know which impurity species is responsible for the reduction of interface traps. The impurities have several effects: (a) The oxidation rate is increased, (b) there is mobile charge present in the oxide in the form of sodium, (c) the trap density at the interface is phenomenally low, but (d) the interface state density can increase during rapid thermal annealing. We fabricated lateral MOSFET transistors in off-axis Si-face 4H-SiC material. MOSFETs made with a gate oxide that includes impurities, and have not received an RTP anneal, show very high peak-mobility values of about 150 cm2/Vs, which is almost two orders of magnitude higher than the one obtained from MOSFETs employing the conventional thermal gate oxide. We find that the field-effect mobility is correlated with the reduction in the interface trap density.