LV*: A Class of Lazy-Versioning HTMs for Low-Cost Integration of Transactional Memory Systems
Paper in proceeding, 2010

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transactional memory

parallel architectures

Author

Anurag Negi

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Mridha Mohammad Waliullah

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Stenström

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Published in

2nd IEEE Int. Forum of Next-Generation Multicore/Many-Core Technologies (IFMT’2010)

art. no 1882460
978-145030008-7 (ISBN)

Categorizing

Subject Categories (SSIF 2011)

Computer and Information Science

Identifiers

DOI

10.1145/1882453.1882460

ISBN

978-145030008-7

More information

Created

10/7/2017