LV*: A Class of Lazy-Versioning HTMs for Low-Cost Integration of Transactional Memory Systems
Paper i proceeding, 2010

Chalmers Library Link Resolver(opens in a new window)|View at Publisher| Export | Download | Add to List | More... ACM International Conference Proceeding Series 2010, Article number 1882460 2nd International Forum on Next Generation Multicore/Manycore Technologies, IFMT'2010, Co-located with the 37th International Symposium on Computer Architecture, ISCA 2010; Saint-Malo; France; 19 June 2010 through 19 June 2010; Code 83375 LV*: A class of lazy versioning HTMs for low-cost integration of transactional memory systems (Conference Paper) Negi, A. , Waliullah, M.M. , Stenstrom, P. Chalmers University of Technology, Gothenburg, Sweden View references (29) Abstract Transactional memory (TM) promises to unlock parallelism in software in a safer and easier way than lock-based approaches but the path to deployment is unclear for several reasons. First of all, since TM has not been deployed in any machine yet, experience of using it is limited. While software transactional memory implementations exist, they are too slow to provide useful experience. Existing hardware transactional memory implementations, on the other hand, can provide the efficiency required but they require a significant effort to integrate in cache coherence infrastructures or freeze critical policy parameters. This paper proposes the LV* (lazy versioning and eager/lazy conflict resolution) class of hardware transactional memory protocols. This class of protocols has been implemented with ease of deployment in mind. LV* can be integrated with low additional complexity in standard snoopy-cache MESI-protocols and can be accommodated in a directory-based cache coherence infrastructure. Since the optimal conflict resolution policy (lazy or eager) depends on transactional characteristics of workloads, LV* supports a set of conflict resolution policies that range from LazEr - a family of Lazy versioning Eager conflict resolution protocols - to LL-MESI which provides lazy resolution. We show that LV* can be hosted in a MESI protocol through straightforward extensions and that the flexibility in the choice of conflict resolution strategy has a significant impact on performance.

transactional memory

parallel architectures


Anurag Negi

Chalmers, Data- och informationsteknik, Datorteknik

Mridha Mohammad Waliullah

Chalmers, Data- och informationsteknik, Datorteknik

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

2nd IEEE Int. Forum of Next-Generation Multicore/Many-Core Technologies (IFMT’2010)

978-145030008-7 (ISBN)


Data- och informationsvetenskap





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