Per Stenström
Visar 193 publikationer
SCALE: Secure and Scalable Cache Partitioning
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem
Bounding the execution time of parallel applications on unrelated multiprocessors
GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases
Federated Scheduling of Sporadic DAGs on Unrelated Multiprocessors
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling
DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors
A GPU Register File using Static Data Compression
SaC: Exploiting execution-time slack to save energy in heterogeneous multicore systems
QoS-driven coordinated management of resources to save energy in multi-core systems
Trends on heterogeneous and innovative hardware and software systems
SimICS/sun4m: A virtual workstation
Global dead-block management for task-parallel programs
Scheduling parallel real-time recurrent tasks on multicore platforms
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
Rock: A framework for pruning the design space of hybrid main memory systems
Runtime-Assisted Global Cache Management for Task-based Parallel Programs
Timing-anomaly free dynamic scheduling of task-based parallel applications
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures
EUROSERVER: Share-anything scale-out micro-server design
A Case for Runtime-Assisted Global Cache Management
RADAR: Run-time assisted Dead-Region Management for Last-Level Caches
Adaptive row addressing for cost-efficient parallel memory protocols in large-capacity memories
ProF: Probabilistic Hybrid Main Memory Management for High Performance and Fairness
RADAR: Runtime-assisted dead region management for last-level caches
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor
Timing-anomaly free dynamic scheduling of task-based parallel applications
Performance Impact of Batching Web Application Requests using Hot-spot Processing on GPUs
A Primer on Compression in the Memory Hierarchy
Enhancing Garbage Collection Synchronization using Explicit Bit Barriers
HyComp: A Hybrid Cache Compression Method for Selection of Data-Type-Specific Compression Methods
RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches
Introduction to the JPDC special issue on Perspectives on Parallel and Distributed Processing
Characterizing and Exploiting Small-Value Memory Instructions
Overhead-Aware Temporal Partitioning on Multicore Processors
A Design-Time Resource Partitioning Method for Hybrid Main Memory
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
Removal of Conflicts in Hardware Transactional Memory Systems
Proceedings of the 2014 ACM International Conference on Supercomputing
A Case for a Value-Aware Cache
Temporal Partitioning on Multicore Platform
Performance and energy analysis of the restricted transactional memory implementation on haswell
Effective Resource Management Towards Efficient Computing
SC2: A statistical compression cache scheme
Runtime-guided cache coherence optimizations in multi-core architectures
Crystal: A design-time resource partitioning method for hybrid main memory
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory
Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)
Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures
HARP: Adaptive Abort Recurrence Prediction for Hardware Transactional Memory
Towards automatic resource management in parallel architectures.
Moving from Petaflops to Petadata
Efficient Forwarding of Producer-Consumer Data in Task-based Programs
Efficient Forwarding of Producer-Consumer Data in Task-based Programs
Transactional prefetching: Narrowing the window of contention in hardware transactional memory
Transactional Prefetching: Narrowing the Window of Contention in Hardware Transactional Memory
Critical lock analysis: Diagnosing critical section bottlenecks in multithreaded applications
Transactions on Architectures and Code Optimizations
Transactional Prefetching: Narrowing the Window of Contention in Hardware Transaction Memory
A Data Forwarding Scheme for Task-based Programming Models
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Implications of Merging Phases on Scalability of Multicore Architectures
Transactions on High Performance and Embedded Architectures and Compilers - Vol 4
A Unified Approach to Eliminate Memory Accesses Early
ZEBRA: A data-centric, hybrid-policy hardware transactional memory design
Coherence-Less Model for Shared-Memory, Speculative Multi-core Processors
The Impact of Non-coherent on Lazy HardwareTransactional Memory Systems
The impact of non-coherent buffers on lazy hardware transactional memory systems
Techniques for Reduction of Conflicts in Hardware Transactional Memory.
Hints Based Speculative Execution for Exploiting Probabilistic Parallel Execution.
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Diagnosing Critical Section Bottlenecks in Multithreaded Applications
Transactions on High-Performance Embedded Architectures and Compilers Vol 3
Transaction on Architectures and Code Optimization
Classification and Elimination of Conflicts in Hardware-Transactional Memory Systems
Implications of Merging Phases on Scalability of Multi-core Architectures
Eager meets lazy: The impact of write-buffering on hardware transactional memory
Semantic Information Driven Speculative Execution
LV*: A Class of Lazy-Versioning HTMs for Low-Cost Integration of Transactional Memory Systems
The VELOX Transactional Memory Stack
Simple Performance Optimization Techniques for Hardware Transactional Memory Systems
Diagnosing Serialization Bottlenecks in Multi-threaded Applications on Multi-core Processors
Generating and Comparing Memory Access Ranges for Speculative Throughput Computing
LV*: A Low Complexity Lazy Versioning HTM Infrastructure
Characterization and Exploitation of Silent Loads
Characterization and Exploitation of Narrow-Width Loads:The Narrow-Width Cache Approach
Sematic based speculative parallel execution.
Transactions on High-Performance Embedded Architectures and Compilers
Zero-Value Caches: Cancelling Loads that Return Zero.
A Flexible Code-Compression Scheme using Partitioned Look-Up Tables
Semantic information driven speculative execution
Cancellation of Loads that Return Zero Using Zero-Value Caches
Zero-Value Caches: Cancelling Loads that Return Zero
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Using Hoarding to Increase the Availability in Shared File Systems
Schemes for avoiding starvation in transactional memory systems
Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors
Simple Penalty-Sensitive Cache Replacement Policies
Zero Loads: Canceling Load Requests by Tracking Zero Values
Accommodation of the Bandwidth of Large Cache Blocks using Cache/Memory Link Compression
A Micro-Architectural Power-Saving Technique for D-NUCA Caches
Reducing Roll-back Overhead in Transactional Memory Systems by Checkpointing Conflicting Accesses
Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems
A Flexible Code Compression Scheme using Partitioned Look-Up Tables
Efficient Management of Speculative Data in Hardware Transactional Memory Systems
Memory Link Compression Schemes: A Value Locality Perspective
Proceedings of the 14th IEEE Symp. on High-Performance Computer Architecture
Leveraging data promotion for low power D-NUCA caches
The worst-case execution-time problem - overview of methods and survey of tools
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Proceedings of the 2007 International Conference on HiPEAC
Implicit Transactional Memory in Kilo-Instruction Processors
Loop-Level Speculative Parallelism in Embedded Applications.
Efficient Management of Speculative Data in Hardware Transactional Memory Systems
An Adaptive Shared/Private NUCA Cache Partiotioning Scheme for Chip Multiprocessors
Effectiveness of Caching in a Distributed Digital Library.
SimWattch: Integrating complete-system and user-level performance and power simulators
The Paradigm Shift to Multi-Cores: Opportunities and Challenges
Exposed Datapath for Efficient Computing
Starvation-Free Transactional Memory System Protocols.
Starvation-Free Commit Arbitration Policies for Transactional Memory Systems.
Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems
Improving Power Efficiency of D-NUCA Caches
Limits on Thread-Level Speculative Parallelism in Embedded Applications
Characterization of Apache web server with Specweb2005
Proceedings of the 2007 ACM International Conference on Computing Frontiers
A Cache Replacement Algorithm based on Frequency and Recency for Chip Multiprocessors.
Starvation-Free Commit Arbitration Policies for Transactional Memory Systems.
Two Threads in the Machine is Better than Eight in the Bush
Exposed Datapath for Efficient Computing
Penalty-Sensitive Replacement Policies for Caches.
Exploitation of Value Locality for Memory Link Compression
Enhancing Lower Level Cache Performance by Early Miss Determination and Bypassing.
Value-Cache Based Compression Schemes for Multiprocessors
High-Performance Embedded Architecture and Compilation Roadmap
A Cache-Partition Aware Replacement Policy for Chip Multiprocessors.
Enhancing Simulation Speed using Matched-Pair Comparison
Keynote 2: The chip-multiprocessing paradigm shift: Opportunities and challenges
A Cost-Effective Memory Organization for Future Servers
Languages Compilers and Tools for Embedded Systems
Implementing Kilo-Instruction Multiprocessors
A Robust Memory Compression Scheme
Reducing Misspeculation Overhead for Module-Level Speculative Execution
Evaluation of Extended Dictionary-Based Static Code Compression Techniques
Self-Correcting LRU Replacement Policies.
A Cache Block Reuse Prediction Scheme
SimWattch: An Approach to Integrate Complete-System with User-Level Performance/Power Simulators
FlexSoC: Combining Flexibility and Efficiency in SoC Designs
An Evaluation of Document Prefetching in a Distributed Digital Library
A Novel Approach to Cache Block Reuse Prediction
Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections
Improving Speculative Thread-Level Parallelism Through Module Run-Length Prediction
Coherence Predictor Cache: A Resource Efficient Coherence Message Prediction Infrastructure.
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
Reducing Misspeculation Overhead for Module-Level Speculative Execution
Evaluation of Document Prefetching in a Distributed Digital Library.
An Evaluation of Document Prefetching in a Distributed Digital Library
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of a Conditional Branch
Improvement of energy-efficiency in off-chip caches by selective prefetching
TLB and Snoop Energy-Reduction using Virtual Caches for Low-Power Chip-Multiprocessors
An All-Software Thread-Level Data Dependence Speculation System for Multiprocessors
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Visar 12 forskningsprojekt
eProcessor: Det europeiska utvidgningsbara, energi-effektiva, storskaliga processor ekosystemet
High Performance and Embedded Architecture and Compilation (HiPEAC5)
TEchnology TRAnsfer via Multinational Application eXperiments (TETRAMAX)
High Performance and Embedded Architecture and Compilation (HiPEAC4)
ACE: Approximativa algoritmer och datorsystem
Meeting Challenges in Computer Architecture (MECCA)
Green Computing Node for European micro-servers (EUROSERVER)
Ramverk för finkornig resurshantering i heterogena parallella arkitekturer
High Performance and Embedded Architecture and Compilation (HiPEAC)