ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
Artikel i vetenskaplig tidskrift, 2014

Transactional contention management policies show considerable variation in relative performance with changing workload characteristics. Consequently, incorporation of fixed-policy Transactional Memory (TM) in general purpose computing systems is suboptimal by design and renders such systems susceptible to pathologies. Of particular concern are Hardware TM (HTM) systems where traditional designs have hardwired policies in silicon. Adaptive HTMs hold promise, but pose major challenges in terms of design and verification costs. In this paper, we present the ZEBRA HTM design, which lays down a simple yet high-performance approach to implement adaptive contention management in hardware. Prior work in this area has associated contention with transactional code blocks. However, we discover that by associating contention with data (cache blocks) accessed by transactional code rather than the code block itself, we achieve a neat match in granularity with that of the cache coherence protocol. This leads to a design that is very simple and yet able to track closely or exceed the performance of the best performing policy for a given workload. ZEBRA, therefore, brings together the inherent benefits of traditional eager HTMs-parallel commits-and lazy HTMs-good optimistic concurrency without deadlock avoidance mechanisms-, combining them into a low-complexity design.

Multicore architectures

parallel programming

cache coherence protocols

transactional memory


Ruben Titos Gil

Chalmers, Data- och informationsteknik, Datorteknik

Anurag Negi

Chalmers, Data- och informationsteknik, Datorteknik

M. E. Acacio

Universidad de Murcia

J. M. García

Universidad de Murcia

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

IEEE Transactions on Parallel and Distributed Systems

1045-9219 (ISSN)

Vol. 25 5 1359-1369


Informations- och kommunikationsteknik


Elektroteknik och elektronik



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