ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
Journal article, 2014
Multicore architectures
parallel programming
cache coherence protocols
transactional memory
Author
Ruben Titos Gil
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Anurag Negi
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
M. E. Acacio
University of Murcia
J. M. García
University of Murcia
Per Stenström
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
IEEE Transactions on Parallel and Distributed Systems
1045-9219 (ISSN) 15582183 (eISSN)
Vol. 25 5 1359-1369Areas of Advance
Information and Communication Technology
Subject Categories
Electrical Engineering, Electronic Engineering, Information Engineering
DOI
10.1109/TPDS.2013.262