Ruben Titos Gil
Showing 12 publications
2015
Hardware approaches to transactional memory in chip multiprocessors
Ruben Titos Gil, M. E. Acacio
Handbook on Data Centers, p. 805-835
Book chapter
2015
Enhancing Garbage Collection Synchronization using Explicit Bit Barriers
Jochen Hollmann, Ruben Titos Gil, Per Stenström
44th International Conference on Parallel Processing, ICPP 2015, Beijing, China, 1-4 September, p. 769 - 778
Paper in proceedings
2014
Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems
E. Gaona, Ruben Titos Gil, J. Fernandez et al
Journal of Supercomputing. Vol. 68 (2), p. 914-934
Journal article
2014
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
Ruben Titos Gil, Anurag Negi, M. E. Acacio et al
IEEE Transactions on Parallel and Distributed Systems. Vol. 25 (5), p. 1359-1369
Journal article
2014
Performance and energy analysis of the restricted transactional memory implementation on haswell
Bhavishya Goel, Ruben Titos Gil, Anurag Negi et al
Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS, p. 615-624
Paper in proceedings
2013
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory
Ruben Titos Gil, Anurag Negi, M. E. Acacio et al
IEEE Transactions on Parallel and Distributed Systems. Vol. 24 (11), p. 2192-2201
Journal article
2013
SCIN-Cache: Fast Speculative Versioning in Multithreaded Cores
Anurag Negi, Ruben Titos Gil
Transactions on Architecture and Code Optimization. Vol. 9 (4)
Journal article
2013
Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory
Ruben Titos Gil, M. E. Acacio, J. M. García
IEEE Transactions on Parallel and Distributed Systems. Vol. 24 (1), p. 59-71
Journal article
2013
Techniques to Improve Performance in Requester-Wins Hardware Transactional Memory
A. Armejach, Ruben Titos Gil, Anurag Negi et al
Transactions on Architecture and Code Optimization. Vol. 10 (4), p. articlenr, 42-
Journal article
2012
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Anurag Negi, Ruben Titos Gil, M. E. Acacio et al
18th IEEE International Symposium on High Performance Computer Architecture (;New Orleans, LA; February 25-29 2012, p. 141-151
Paper in proceedings
2011
The impact of non-coherent buffers on lazy hardware transactional memory systems
Anurag Negi, Ruben Titos Gil, M. E. Acacio et al
IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 25th IEEE International Parallel and Distributed Processing Symposium, Workshops and Phd Forum, IPDPSW 2011; Anchorage, AK; 16 May 2011 through 20 May 2011, p. 700-707
Paper in proceedings
2011
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Anurag Negi, Per Stenström, Ruben Titos Gil et al
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT (Article number 6113816), p. 203-204
Paper in proceedings
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