Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory
Journal article, 2013

Hardware transactional memory (HTM) designs are very sensitive to the manner in which speculative updates from transactions are handled in the system. This study highlights how the lack of effective techniques for store management results in a quick degradation in the performance of eager HTM systems with increasing contention and, thus, lends credence to the belief that eager designs do not perform as well as their lazy counterparts when conflicts abound. In this work, we present two simple ways to improve handling of speculative stores-a way to effectively manage lines that exhibit migratory sharing and a way to hide store latency, particularly for those stores that target contended cache lines owned by other concurrent transactions. These two mechanisms yield substantial improvements in execution time when running applications with high contention, allowing eager designs to exceed the performance of lazy ones. Interestingly, the benefits that accrue from these enhancements can be at par with those achieved using more complex system-wide HTM techniques. Coupled with the fact that eager designs are easier to integrate into cache coherent architectures than lazy ones, we claim that with judicious management of stores they represent a more compelling design alternative.

transactional memory

multicore architectures

Parallel programming





Ruben Titos Gil

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Anurag Negi

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

M. E. Acacio

University of Murcia

J. M. García

University of Murcia

Per Stenström

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

IEEE Transactions on Parallel and Distributed Systems

1045-9219 (ISSN)

Vol. 24 11 2192-2201

Subject Categories

Computer and Information Science



More information