Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory
Journal article, 2013
transactional memory
multicore architectures
Parallel programming
coherence
performance
caches
Author
Ruben Titos Gil
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Anurag Negi
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
M. E. Acacio
University of Murcia
J. M. García
University of Murcia
Per Stenström
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
IEEE Transactions on Parallel and Distributed Systems
1045-9219 (ISSN) 15582183 (eISSN)
Vol. 24 11 2192-2201 6342882Subject Categories
Computer and Information Science
DOI
10.1109/tpds.2012.315