SCIN-Cache: Fast Speculative Versioning in Multithreaded Cores
Journal article, 2013
This article describes cache designs for efficiently supporting speculative techniques like transactional memory on chip multiprocessors with multithreaded cores. On-demand allocation and prompt freeing of speculative cache space in the design reduces the burden on nonspeculative execution. Quick access to both clean and speculative versions of data for multiple contexts provides flexibility and greater design freedom to HTM architects. Performance analysis shows the designs stand up well against other HTM design proposals, with potential performance gains in high contention applications with small transactions.
speculation support
hardware transactional memory
coherence
processors
Design
Performance
hardware transactional memory
consistency
Cache design
Author
Anurag Negi
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Ruben Titos Gil
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Transactions on Architecture and Code Optimization
1544-3566 (ISSN) 1544-3973 (eISSN)
Vol. 9 4 58High Performance and Embedded Architecture and Compilation (HiPEAC)
European Commission (EC) (EC/FP7/287759), 2012-01-01 -- 2015-12-31.
Subject Categories
Computer and Information Science
DOI
10.1145/2400682.2400717