SCIN-Cache: Fast Speculative Versioning in Multithreaded Cores
Artikel i vetenskaplig tidskrift, 2013

This article describes cache designs for efficiently supporting speculative techniques like transactional memory on chip multiprocessors with multithreaded cores. On-demand allocation and prompt freeing of speculative cache space in the design reduces the burden on nonspeculative execution. Quick access to both clean and speculative versions of data for multiple contexts provides flexibility and greater design freedom to HTM architects. Performance analysis shows the designs stand up well against other HTM design proposals, with potential performance gains in high contention applications with small transactions.

speculation support

hardware transactional memory

coherence

processors

Design

Performance

hardware transactional memory

consistency

Cache design

Författare

Anurag Negi

Chalmers, Data- och informationsteknik, Datorteknik

Ruben Titos Gil

Chalmers, Data- och informationsteknik, Datorteknik

Transactions on Architecture and Code Optimization

1544-3566 (ISSN) 1544-3973 (eISSN)

Vol. 9 4

High Performance and Embedded Architecture and Compilation (HiPEAC)

Europeiska kommissionen (FP7), 2012-01-01 -- 2015-12-31.

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1145/2400682.2400717

Mer information

Skapat

2017-10-08