The impact of non-coherent buffers on lazy hardware transactional memory systems
Paper in proceedings, 2011

When supported in silicon, transactional memory (TM) promises to become a fast, simple and scalable parallel programming paradigm for future shared memory multiprocessor systems. Among the multitude of hardware TM design points and policies that have been studied so far, lazy conflict resolution designs often extract the most concurrency, but their inherent need for lazy versioning requires careful management of speculative updates. In this paper we study how coherent buffering, in private caches for example, as has been proposed in several hardware TM proposals, can lead to inefficiencies. We then show how such inefficiencies can be substantially mitigated by using complete or partial non-coherent buffering of speculative writes in dedicated structures or suitably adapted standard per-core write-buffers. These benefits are particularly noticeable in scenarios involving large coarse grained transactions that may write a lot of non-contended data in addition to actively shared data. We believe our analysis provides important insights into some overlooked aspects of TM behaviour and would prove useful to designers wishing to implement lazy TM schemes in hardware. © 2011 IEEE.

Author

Anurag Negi

University of Murcia

Ruben Titos Gil

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

M. E. Acacio

Chalmers

J. M. García

University of Murcia

Per Stenström

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 25th IEEE International Parallel and Distributed Processing Symposium, Workshops and Phd Forum, IPDPSW 2011; Anchorage, AK; 16 May 2011 through 20 May 2011

700-707

Subject Categories

Computer and Information Science

DOI

10.1109/IPDPS.2011.205

ISBN

978-076954385-7

More information

Latest update

9/10/2018