Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Paper in proceeding, 2011
Concurrency
Multicores
Transactional memory
Author
Anurag Negi
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Per Stenström
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Ruben Titos Gil
University of Murcia
M. E. Acacio
University of Murcia
J. M. García
University of Murcia
Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
1089795X (ISSN)
Article number 6113816 203-204 6113816978-076954566-0 (ISBN)
Subject Categories
Computer Engineering
Areas of Advance
Information and Communication Technology
DOI
10.1109/PACT.2011.41
ISBN
978-076954566-0