Cancellation of Loads that Return Zero Using Zero-Value Caches
Poster (konferens), 2009

The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads — loads accessing memory locations that contain the value “zero” — to improve performance and energy dissipation. Our study shows that such loads comprise as many as 18% of the total number of dynamic loads. We show that a significant fraction of zero loads ends up on the critical memory-access path in out-of-order cores. We propose a non-speculative microarchitectural technique — Zero-Value Cache (ZVC) — to capitalize on zero loads and explore critical design options of such caches. We show that with modest investment (typically a 512-byte structure), we can obtain speedups up to 32%. Most importantly, zero-value caches never cause performance loss.

Frequent Value Locality

Load Criticality

Zero Load



Mafijul Islam

Chalmers, Data- och informationsteknik, Datorteknik

Sally A McKee

Chalmers, Data- och informationsteknik, Datorteknik

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

23rd International Conference on Supercomputing, ICS'09; Yorktown Heights, NY; United States; 8 June 2009 through 12 June 2009




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