Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Paper i proceeding, 2012

Lazy hardware transactional memory has been shown to be more efficient at extracting available concurrency than its eager counterpart. However, it poses scalability challenges at commit time as existence of conflicts among concurrent transactions is not known prior to commit. Non-conflicting transactions may have to wait before committing, severely affecting performance in certain workloads. Early conflict detection can be employed to allow such transactions to commit simultaneously. In this paper we show that the potential of this technique has not yet been fully utilized, with design choices in prior work severely burdening common-case transactional execution to avoid some relatively uncommon correctness concerns. The paper quantifies the severity of the problem and develops. pi-TM, an early conflict detection - lazy conflict resolution design. This design highlights how, with modest extensions to existing directory-based coherence protocols, information regarding possible conflicts can be effectively used to achieve true parallelism at commit without burdening the common-case. We leverage the observation that contention is typically seen on only a small fraction of shared data accessed by coarse-grained transactions. Pessimistic invalidation of such lines when committing or aborting, therefore, enables fast common-case execution. Our results show that. pi-TM performs consistently well and, in particular, far better than previous work on early conflict detection in lazy HTM. We also identify a pathological scenario that lazy designs with early conflict detection suffer from and propose a simple hardware workaround to sidestep it.

Coherence protocol

Conflict detection

Conflict Resolution

Shared data

Concurrent transactions


Transactional memory


Anurag Negi

Chalmers, Data- och informationsteknik, Datorteknik

Ruben Titos Gil

Universidad de Murcia

M. E. Acacio

Universidad de Murcia

J. M. García

Universidad de Murcia

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

Proceedings - International Symposium on High-Performance Computer Architecture

15300897 (ISSN)

978-146730824-3 (ISBN)


Informations- och kommunikationsteknik


Data- och informationsvetenskap





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