Improvement of energy-efficiency in off-chip caches by selective prefetching
Artikel i vetenskaplig tidskrift, 2002

The line size/performance trade-offs in off-chip second-level caches in light of energy-efficiency are revisited. Based on a mix of applications representing server and mobile computer system usage, we show that while the large line sizes (128 bytes) typically used maximize performance, they result in a high power dissipation owing to the limited exploitation of spatial locality. In contrast, small blocks (32 bytes) are found to cut the energy-delay by more than a factor of 2 with only a moderate performance loss of less than 25%. As a remedy, prefetching, if applied selectively, is shown to avoid the performance losses of small blocks, yet keeping power consumption low.

prefetching

energy-delay

performance evaluation

energy-efficiency

caches

Författare

Jonas Jalminger

Chalmers, Institutionen för datorteknik

Per Stenström

Chalmers, Institutionen för datorteknik

Microprocessors and Microsystems

0141-9331 (ISSN)

Vol. 26 107-121

Ämneskategorier

Datorteknik

DOI

10.1016/S0141-9331(01)00150-8