A Case for a Value-Aware Cache
Artikel i vetenskaplig tidskrift, 2014

Replication of values causes poor utilization of on-chip cache memory resources. This paper addresses the question: How much cache resources can be theoretically and practically saved if value replication is eliminated? We introduce the concept of value-aware caches and show that a sixteen times smaller value-aware cache can yield the same miss rate as a conventional cache. We then make a case for a value-aware cache design using Huffman-based compression. Since the value set is rather stable across the execution of an application, one can afford to reconstruct the coding tree in software. The decompression latency is kept short by our proposed novel pipelined Huffman decoder that uses canonical codewords. While the (loose) upper-bound compression factor is 5.2X, we show that, by eliminating cache-block alignment restrictions, it is possible to achieve a compression factor of 3.4X for practical designs.

Författare

Angelos Arelakis

Chalmers, Data- och informationsteknik, Datorteknik

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

IEEE Computer Architecture Letters

1556-6056 (ISSN)

Vol. 13 1-4

Styrkeområden

Informations- och kommunikationsteknik

Ämneskategorier

Annan teknik

Elektroteknik och elektronik

DOI

10.1109/L-CA.2012.31