Zero-Value Caches: Cancelling Loads that Return Zero.
Paper i proceeding, 2009

The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads. loads accessing memory locations that contain the to improve performance and energy dissipation. Our study shows that such loads comprise as many as 18% of the total number of dynamic loads. We show that a significant fraction of zero loads ends up on the critical memory-access path in out-oforder cores. We propose a non-speculative microarchitectural technique. Zero-Value Cache (ZVC). to capitalize on zero loads and explore critical design options of such caches. We show that with modest investment, we can obtain speedups up to 78% and reduce the overall energy dissipation by up to 39%. Most importantly, zero-value caches never cause performance loss.


Mafijul Islam

Chalmers, Data- och informationsteknik, Datorteknik

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

1089795X (ISSN)

237-245 5260542
978-076953771-9 (ISBN)


Data- och informationsvetenskap





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