Eager meets lazy: The impact of write-buffering on hardware transactional memory
Paper i proceeding, 2011
Execution time
Design points
Interfacial structures
Management policy
Prefetches
Structural optimization
Workload characteristics
Conflict Resolution
Structural design
Parallel architectures
Memory hierarchy
Versioning
Detailed modeling
Sound designs
Storage allocation (computer)
Chip-multiprocessing
Processor cores
Transactional memory
Relative performance
Författare
Anurag Negi
Chalmers, Data- och informationsteknik, Datorteknik
R. Titos-Gil
Universidad de Murcia
M. E. Acacio
Universidad de Murcia
J. M. García
Universidad de Murcia
Per Stenström
Chalmers, Data- och informationsteknik, Datorteknik
Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, 13-16 September 2011
0190-3918 (ISSN)
73-82978-076954510-3 (ISBN)
Ämneskategorier
Data- och informationsvetenskap
DOI
10.1109/ICPP.2011.63
ISBN
978-076954510-3