Eager meets lazy: The impact of write-buffering on hardware transactional memory
Paper i proceeding, 2011

Hardware transactional memory (HTM) systems have been studied extensively along the dimensions of speculative versioning and contention management policies. The relative performance of several designs policies has been discussed at length in prior work within the framework of scalable chipmultiprocessing systems. Yet, the impact of simple structural optimizations like write-buffering has not been investigated and performance deviations due to the presence or absence of these optimizations remains unclear. This lack of insight into the effective use and impact of these interfacial structures between the processor core and the coherent memory hierarchy forms the crux of the problem we study in this paper. Through detailed modeling of various write-buffering configurations we show that they play a major role in determining the overall performance of a practical HTM system. Our study of both eager and lazy conflict resolution mechanisms in a scalable parallel architecture notes a remarkable convergence of the performance of these two diametrically opposite design points when write buffers are introduced and used well to support the common case. Mitigation of redundant actions, fewer invalidations on abort, latency-hiding and prefetch effects contribute towards reducing execution times for transactions. Shorter transaction durations also imply a lower contention probability, thereby amplifying gains even further. The insights, related to the interplay between buffering mechanisms, system policies and workload characteristics, contained in this paper clearly distinguish gains in performance to be had from write-buffering from those that can be ascribed to HTM policy. We believe that this information would facilitate sound design decisions when incorporating HTMs into parallel architectures.

Execution time

Design points

Interfacial structures

Management policy


Structural optimization

Workload characteristics

Conflict Resolution

Structural design

Parallel architectures

Memory hierarchy


Detailed modeling

Sound designs

Storage allocation (computer)


Processor cores

Transactional memory

Relative performance


Anurag Negi

Chalmers, Data- och informationsteknik, Datorteknik

R. Titos-Gil

Universidad de Murcia

M. E. Acacio

Universidad de Murcia

J. M. García

Universidad de Murcia

Per Stenström

Chalmers, Data- och informationsteknik, Datorteknik

Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, 13-16 September 2011

0190-3918 (ISSN)

978-076954510-3 (ISBN)


Data- och informationsvetenskap





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