Eager meets lazy: The impact of write-buffering on hardware transactional memory
Paper in proceeding, 2011
Execution time
Design points
Interfacial structures
Management policy
Prefetches
Structural optimization
Workload characteristics
Conflict Resolution
Structural design
Parallel architectures
Memory hierarchy
Versioning
Detailed modeling
Sound designs
Storage allocation (computer)
Chip-multiprocessing
Processor cores
Transactional memory
Relative performance
Author
Anurag Negi
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
R. Titos-Gil
University of Murcia
M. E. Acacio
University of Murcia
J. M. García
University of Murcia
Per Stenström
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, 13-16 September 2011
0190-3918 (ISSN)
73-82978-076954510-3 (ISBN)
Subject Categories
Computer and Information Science
DOI
10.1109/ICPP.2011.63
ISBN
978-076954510-3