Benchmarking the Hardware Error Sensitivity of Machine Instructions
Paper in proceedings, 2013

This paper presents the results of an extensive fault injection study of the impact of processor faults that manifest as bit flip errors in instruction set architecture registers and main memory locations. The aim is to investigate if bit errors that propagate to the source registers or memory locations of a given class of machine instructions have a similar probability of generating undetected value failures (i.e., silent data corruptions) for different programs. The results show a fairly large variation in the error sensitivity over different programs for all classes of machine instructions, which indicates that the effectiveness of error mitigation techniques that target specific machine instructions may vary significantly for different programs.

machine instructions

fault injection

hardware error sensitivity

single bit-flips

soft error.

Author

Behrooz Sangchoolie

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Fatemeh Ayatolahi

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Roger Johansson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Johan Karlsson

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings of the 2013 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 9)

Subject Categories

Embedded Systems

Computer Systems

More information

Created

10/6/2017