A Proof-Producing Translator for Verilog Development in HOL
Paper in proceeding, 2019
hardware verification
interactive theorem proving
verilog
Author
Andreas Lööw
Chalmers, Computer Science and Engineering (Chalmers), Formal methods
Magnus Myreen
Chalmers, Computer Science and Engineering (Chalmers), Formal methods
Proceedings - 2019 IEEE/ACM 7th International Workshop on Formal Methods in Software Engineering, FormaliSE 2019
99-108 8807452
Montreal, Canada,
Subject Categories
Language Technology (Computational Linguistics)
Embedded Systems
Computer Systems
DOI
10.1109/FormaliSE.2019.00020