Low-Power HEMT LNAs for Quantum Computing

Doctoral thesis, 2025

Future superconducting quantum systems must scale up to millions of qubits to solve complex problems beyond classical capabilities. Due to the limited cooling capacity at cryogenic temperatures, large-scale integration places strict demands on the qubit readout chain, in particular with respect to noise and dc power consumption. HEMT LNAs operating at 4 K have become essential in superconducting qubit readout due to their superior noise characteristics. This thesis addresses the challenge of minimizing power dissipation in HEMT LNAs by combining low-power transistor modeling, circuit design, and new noise characterization methodologies used for pulse-operated strategies.

At the device and circuit level, a small-signal noise model of cryogenic InP HEMTs was developed and extracted down to 1 μW, which revealed optimized bias points at minimal power without sacrificing noise performance. Leveraging this model, a hybrid HEMT LNA optimized for superconducting qubit readout was designed, fabricated, and measured, achieving a record-low power dissipation of 100 μW while maintaining a noise temperature of 2.0 K at 4–6 GHz.

By analyzing the conditions for qubit readout, a HEMT LNA for pulsed operation was proposed based on dynamic activation only during qubit measurement windows. To characterize the dynamic behavior, novel time-domain noise measurement techniques with nanosecond-scale resolution were developed. A cryogenic time-domain noise measurement setup with 5 ns time resolution and sub-0.3 K noise standard deviation, was implemented and investigated. Using this system, the transient noise response of gate-switched HEMT LNAs was studied under a quantum error correction scenario. A fast-recovery bias waveform, developed through a genetic algorithm, successfully reduced noise recovery time to 35 ns, demonstrating HEMT LNA power dissipation proportional to the selected duty cycle without penalty in neither noise nor gain compared to static operation.