Efficacy of Pipelining to Reduce Energy of Floating-Point Adders and Multipliers

Paper in proceeding, 2026

Because of the way arithmetic circuits are logically implemented, spurious transitions (glitches) can dominate the energy dissipation of combinational implementations. Insertion of pipeline registers effectively suppresses glitches, but this comes with an energy overhead. To identify in what design situations pipelining reduces energy, we consider adders and multipliers for three different floating-point formats: One 32-bit (FP32) and two 16-bit formats (FP16 and bfloat16) that have different exponent and significand field widths. Each circuit is implemented in a predictive 7-nm FinFET technology and evaluated in terms of gate and signal-transition distributions and energy-delay products. Our evaluations show that, regardless of format, adders benefit more from pipelining than multipliers. Assuming constant timing constraints, pipelining can reduce total adder energy by half for formats with longer significands, but less, around 40%, for bfloat16 which has a short significand. Since combinational adders have larger logic depths than multipliers, an additional positive effect of pipelining is that the timing of the adder becomes more balanced with the multiplier.