High-Efficiency LDMOS Power-Amplifier Design at 1 GHz Using an Optimized Transistor Model
Journal article, 2009

A 10-W LDMOS harmonically tuned power amplifier at 1 GHz with state-of-the-art power-added efficiency (PAE) of 80% is presented. The fundamental and second-harmonic load impedances are optimized for maximum efficiency while other harmonics are blocked by a lowpass load network. A simplified model of the transistor specialized for harmonically tuned and switched mode operations is proposed and used for the design. Good agreement between simulations and measurements is observed, indicating high accuracy of the model and design approach for these particular applications.

harmonically tuned

switched mode

Power amplifier

LDMOS

Author

Hossein Mashad Nemati

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Christian Fager

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Mattias Thorsell

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Herbert Zirath

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

IEEE Transactions on Microwave Theory and Techniques

0018-9480 (ISSN)

Vol. 57 7 1647-1654

Subject Categories

Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/TMTT.2009.2022590

More information

Created

10/8/2017