High-Efficiency LDMOS Power-Amplifier Design at 1 GHz Using an Optimized Transistor Model
Artikel i vetenskaplig tidskrift, 2009

A 10-W LDMOS harmonically tuned power amplifier at 1 GHz with state-of-the-art power-added efficiency (PAE) of 80% is presented. The fundamental and second-harmonic load impedances are optimized for maximum efficiency while other harmonics are blocked by a lowpass load network. A simplified model of the transistor specialized for harmonically tuned and switched mode operations is proposed and used for the design. Good agreement between simulations and measurements is observed, indicating high accuracy of the model and design approach for these particular applications.

harmonically tuned

switched mode

Power amplifier

LDMOS

Författare

Hossein Mashad Nemati

Chalmers, Mikroteknologi och nanovetenskap (MC2), Mikrovågselektronik

Christian Fager

Chalmers, Mikroteknologi och nanovetenskap (MC2), Mikrovågselektronik

Mattias Thorsell

Chalmers, Mikroteknologi och nanovetenskap (MC2), Mikrovågselektronik

Herbert Zirath

Chalmers, Mikroteknologi och nanovetenskap (MC2), Mikrovågselektronik

IEEE Transactions on Microwave Theory and Techniques

0018-9480 (ISSN)

Vol. 57 7 1647-1654

Ämneskategorier

Elektroteknik och elektronik

DOI

10.1109/TMTT.2009.2022590

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2017-10-08