Viterbi Accelerator for Embedded Processor Datapaths
Paper in proceedings, 2012

We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an embedded processor. We investigate the accelerator’s impact on processor performance by using the EEMBC Viterbi benchmark and the in-house Viterbi Branch Metric kernel. Our evaluation based on the EEMBC benchmark shows that an accelerated 65-nm 2.7-ns processor datapath is 20% larger but 90% more cycle efficient than a datapath lacking the Viterbi accelerator, leading to an 87% overall energy reduction and a data throughput of 3.52 Mbit/s.

hardware/software codesign

embedded processor

energy efficiency

Viterbi decoding

accelerator

Author

Muhammad Waqar Azhar

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Magnus Själander

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Ali Hasan

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Akshay Vijayashekar

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Tung Hoang

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Kashan Khurshid Ansari

Chalmers, Computer Science and Engineering (Chalmers)

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

10636862 (ISSN)

133-140 6341463

Areas of Advance

Information and Communication Technology

Energy

Driving Forces

Sustainable development

Subject Categories

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/ASAP.2012.24

ISBN

978-076954768-8

More information

Created

10/7/2017