Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage
Paper in proceedings, 2004

We consider gate leakage next to subthreshold leakage currents in power-saving techniques for future CMOS circuits. Two recently introduced power cut-off techniques are analyzed and compared with respect to the total leakage current using Berkeley PTM. The results show that the efficiency of techniques having logic circuits alternately connected to external supply and ground can drastically de,grade when gate tunneling currents become significant.

Author

Mindaugas Drazdziulis

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

Per Larsson-Edefors

Chalmers, Department of Computer Engineering, Integrated Electronic Systems

2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004

0271-4310 (ISSN)

II745-II748

Subject Categories

Computer and Information Science

DOI

10.1109/ISCAS.2004.1329379

More information

Created

10/7/2017