Practical Way Halting by Speculatively Accessing Halt Tags
Paper in proceedings, 2016

Conventional set-associative data cache accesses waste energy since tag and data arrays of several ways are simultaneously accessed to sustain pipeline speed. Different access techniques to avoid activating all cache ways have been previously proposed in an effort to reduce energy usage. However, a problem that many of these access techniques have in common is that they need to access different cache memory portions in a sequential manner, which is difficult to support with standard synchronous SRAM memory. We propose the speculative halt-tag access (SHA) approach, which accesses low-order tag bits, i.e., the halt tag, in the address generation stage instead of the SRAM access stage to eliminate accesses to cache ways that cannot possibly contain the data. The key feature of our SHA approach is that it determines which tag and data arrays need to be accessed early enough for conventional SRAMs to be used. We evaluate the SHA approach using a 65-nm processor implementation running MiBench benchmarks and find that it on average reduces data access energy by 25.6%.

Author

Daniel Moreau

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Alen Bardizbanyan

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Magnus Själander

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

David Whalley

Florida State University

Per Larsson-Edefors

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 14-18 March 2016

1530-1591 (ISSN)

1375-1380

Areas of Advance

Information and Communication Technology

Driving Forces

Sustainable development

Subject Categories

Computer Systems

ISBN

978-3-9815-3706-2

More information

Created

10/7/2017