Efficient and Flexible Embedded Systems and Datapath Components
Doktorsavhandling, 2008

The comfort of our daily lives has come to rely on a vast number of embedded systems, such as mobile phones, anti-spin systems for cars, and high-definition video. To improve the end-user experience at often stringent require- ments, in terms of high performance, low power dissipation, and low cost, makes these systems complex and nontrivial to design. This thesis addresses design challenges in three different areas of embedded systems. The presented FlexCore processor intends to improve the programmability of heterogeneous embedded systems while maintaining the performance of application-specific accelerators. This is achieved by integrating accelerators into the datapath of a general-purpose processor in combination with a wide control word consisting of all control signals in a FlexCore’s datapath. Furthermore, a FlexCore processor utilizes a flexible interconnect, which together with the expressiveness of the wide control word improves its performance. When designing new embedded systems it is important to have efficient components to build from. Arithmetic circuits are especially important, since they are extensively used in all applications. In particular, integer multipliers present big design challenges. The proposed twin-precision technique makes it possible to improve both throughput and power of conventional integer multipliers, when computing narrow-width multiplications. The thesis also shows that the Baugh-Wooley algorithm is more suitable for hardware implementations of signed integer multipliers than the commonly used modified-Booth algorithm. A multi-core architecture is a common design choice when a single-core architecture cannot deliver sufficient performance. However, multi-core architectures introduce their own design challenges, such as scheduling applications onto several cores. This thesis presents a novel task management unit, which offloads task scheduling from the conventional cores of a multi-core system, thus improving both performance and power efficiency of the system. This thesis proposes novel solutions to a number of relevant issues that need to be addressed when designing embedded systems.

Flexible

Twin-Precision

Scheduling

Embedded

Multiplier

Multi-Core

Opponent: Professor Christian Piguet

Författare

Magnus Själander

Chalmers, Data- och informationsteknik, Datorteknik

An Efficient Twin-Precision Multiplier

International Conference on Computer Design (ICCD),; (2004)p. 30-33

Paper i proceeding

A Flexible Datapath Interconnect for Embedded Applications

IEEE Computer Society Annual Symposium on VLSI,; (2007)p. 15-20

Paper i proceeding

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing

Journal of Signal Processing Systems,; Vol. 57(2009)p. 5-19

Artikel i vetenskaplig tidskrift

A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures

11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008; Parma; Italy; 3 September 2008 through 5 September 2008,; (2008)p. 149-157

Paper i proceeding

Multiplication Acceleration through Twin Precision

IEEE Transactions on Very Large Scale Integration (VLSI) Systems,; Vol. 17(2009)p. 1233-1246

Artikel i vetenskaplig tidskrift

A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

IEEE International Symposium on Circuits and Systems,; (2005)p. 1654-7

Paper i proceeding

Ämneskategorier

Datorteknik

ISBN

978-91-7385-137-4

Technical report D - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University: 40

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 2818

Opponent: Professor Christian Piguet