Magnus Själander

Visar 52 publikationer

2017

CREEP: Chalmers RTL-based Energy Evaluation of Pipelines

Daniel Moreau, Alen Bardizbanyan, Magnus Själander et al
Rapport
2017

Data filter cache designs for enhancing energy efficiency and performance in computing systems

David Whalley, Magnus Själander, Alen Bardizbanyan et al
Patent
2017

Systems and methods for improving processor efficiency through caching

David Whalley, Magnus Själander, Alen Bardizbanyan et al
Patent
2016

Practical Way Halting by Speculatively Accessing Halt Tags

Daniel Moreau, Alen Bardizbanyan, Magnus Själander et al
19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 14-18 March 2016, p. 1375-1380
Paper i proceeding
2016

Redesigning a tagless access buffer to require minimal ISA changes

Carlos Sanchez, Peter Gavin, Daniel Moreau et al
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2016, p. Article number 2968504-
Paper i proceeding
2015

Improving Data Access Efficiency by Using Context-Aware Loads and Stores

Alen Bardizbanyan, Magnus Själander, David Whalley et al
SIGPLAN Notices (ACM Special Interest Group on Programming Languages). Vol. 50 (5), p. 27-36
Paper i proceeding
2013

Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)

Alen Bardizbanyan, Peter Gavin, David Whalley et al
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2013, p. 269-279
Paper i proceeding
2013

Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance

Alen Bardizbanyan, Magnus Själander, David Whalley et al
Transactions on Architecture and Code Optimization. Vol. 10 (4), p. 25 pages-
Artikel i vetenskaplig tidskrift
2013

Towards a Performance- and Energy-Efficient Data Filter Cache

Alen Bardizbanyan, Magnus Själander, David Whalley et al
Workshop on Optimizations for DSP and Embedded Systems (ODES), Proceedings of International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27,, p. 21-28
Paper i proceeding
2013

FlexCore: Implementing an Exposed Datapath Processor

Magnus Själander, Per Larsson-Edefors
Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Samos, Greece, July 15-18, p. 306-313
Paper i proceeding
2013

Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches

Alen Bardizbanyan, Magnus Själander, David Whalley et al
Proceedings of IEEE International Conference on Computer Design (ICCD), Asheville, NC, USA, October 6-9 2013, p. 302-308
Paper i proceeding
2012

An LTE Uplink Receiver PHY Benchmark and Subframe-Based Power Management

Magnus Själander, Sally A McKee, Peter Brauer et al
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software
Paper i proceeding
2012

Configurable RTL Model for Level-1 Caches

Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander et al
Proceedings of NORCHIP, Copenhagen, Denmark, Nov. 11-12
Paper i proceeding
2012

Viterbi Accelerator for Embedded Processor Datapaths

Muhammad Waqar Azhar, Magnus Själander, Ali Hasan et al
Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, p. 133-140
Paper i proceeding
2012

Techniques to Measure, Model, and Manage Power

Bhavishya Goel, Sally A McKee, Magnus Själander
Advances in Computers. Vol. 87, p. 7-54
Kapitel i bok
2011

Infrastructures for Measuring Power

Bhavishya Goel, Magnus Själander, Sally A McKee et al
Rapport
2011

Declarative, SAT-solver-based Scheduling for an Embedded Architecture with a Flexible Datapath

Nikita Frolov, Magnus Själander, Per Larsson-Edefors et al
Swedish System-on-Chip Conference
Konferensbidrag (offentliggjort, men ej förlagsutgivet)
2011

A SAT-Based Compiler for FlexCore

Nikita Frolov, Magnus Själander, Per Larsson-Edefors et al
Rapport
2011

Adapt or Become Extinct!

Georgios Goumas, Sally A McKee, Magnus Själander et al
Proceedings of the 1st International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era, p. 46-51
Paper i proceeding
2011

Power-Aware Resource Scheduling in Base Stations

Magnus Själander, Sally A McKee, Bhavishya Goel et al
Proceedings of the 19th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems Singapore; 25 July 2011 through 27 July 2011, p. 462-465
Paper i proceeding
2011

Reconfigurable Instruction Decoding for a Wide-Control-Word Processor

Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors
Proceedings of Reconfigurable Architectures Workshop (RAW), IEEE International Parallel & Distributed Processing Symposium (IPDPS), p. 322-325
Paper i proceeding
2011

FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation

KASYAB PARMESH SUBRAMANIYAN, Erik J Ryman, Magnus Själander et al
Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), p. 37-40
Paper i proceeding
2011

Early results from ERA embedded reconfigurable architectures

S. Wong, Anthony Brandon, F. Anjam et al
9th IEEE International Conference on Industrial Informatics, INDIN 2011, Lisbon, 26-29 July 2011, p. 816-822
Paper i proceeding
2010

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit

Tung Hoang, Magnus Själander, Per Larsson-Edefors
IEEE Transactions on Circuits and Systems I: Regular Papers. Vol. 57 (12), p. 3073-3081
Artikel i vetenskaplig tidskrift
2010

Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect

Tung Hoang, Ulf Jälmbrant, Erik der Hagopian et al
Proceedings of IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP), p. 55-62
Paper i proceeding
2010

FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation

Erik J Ryman, KASYAB PARMESH SUBRAMANIYAN, Tung Hoang et al
CDNLive! EMEA
Paper i proceeding
2009

A Flexible Code-Compression Scheme using Partitioned Look-Up Tables

Martin Thuresson, Magnus Själander, Per Stenström
Lecture Notes in Computer Science, p. 95-109
Paper i proceeding
2009

Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements

Tung Hoang, Magnus Själander, Per Larsson-Edefors
23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009; Rome; Italy; 23 May 2009 through 29 May 2009
Paper i proceeding
2009

Scheduling for an Embedded Architecture with a Flexible Datapath

Thomas Schilling, Magnus Själander, Per Larsson-Edefors
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), p. 151-156
Paper i proceeding
2009

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing

Martin Thuresson, Magnus Själander, Magnus Björk et al
Journal of Signal Processing Systems. Vol. 57 (1), p. 5-19
Artikel i vetenskaplig tidskrift
2009

Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree

Patrik Kimfors, Niklas Broman, Andreas Haraldsson et al
Proceedings of IEEE International Conference of Electronics, Circuits and Systems
Paper i proceeding
2009

Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture

Tung Hoang, Magnus Själander, Per Larsson-Edefors
Swedish System-on-Chip Conference (SSoCC)
Konferensbidrag (offentliggjort, men ej förlagsutgivet)
2009

Design-Time Scheduling for Processor Exploration

Ulf Jälmbrant, Erik der Hagopian, Magnus Själander et al
Swedish System-on-Chip Conference (SSoCC)
Konferensbidrag (offentliggjort, men ej förlagsutgivet)
2009

High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture

Tung Hoang, Magnus Själander, Per Larsson-Edefors
Proceedings of IEEE Intl SoC Conference (SoCC), p. 119-122
Paper i proceeding
2009

Multiplication Acceleration through Twin Precision

Magnus Själander, Per Larsson-Edefors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 17 (9), p. 1233-1246
Artikel i vetenskaplig tidskrift
2008

High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree

Magnus Själander, Per Larsson-Edefors
15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008; St. Julian's; Malta; 31 August 2008 through 3 September 2008, p. 33-36
Paper i proceeding
2008

Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors

Mafijul Islam, Magnus Själander, Per Stenström
Microprocessors and Microsystems, Elsevier. Vol. 42 (4), p. 183-196
Artikel i vetenskaplig tidskrift
2008

Double Throughput MAC for Performance Enhancement of the FlexCore Processor

Tung Hoang, Magnus Själander, Per Larsson-Edefors
Swedish System-on-Chip Conference
Konferensbidrag (offentliggjort, men ej förlagsutgivet)
2008

Efficient and Flexible Embedded Systems and Datapath Components

Magnus Själander
Doktorsavhandling
2008

The Case for HPM-Based Baugh-Wooley Multipliers

Magnus Själander, Per Larsson-Edefors
Rapport
2008

A Flexible Code Compression Scheme using Partitioned Look-Up Tables

Martin Thuresson, Magnus Själander, Per Stenström
Rapport
2008

A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures

Magnus Själander, Andrei Terechko, Marc Duranton
11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008; Parma; Italy; 3 September 2008 through 5 September 2008, p. 149-157
Paper i proceeding
2007

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing

Martin Thuresson, Magnus Själander, Magnus Björk et al
IEEE SAMOS 2007, p. 18-25
Paper i proceeding
2007

A Flexible Datapath Interconnect for Embedded Applications

Magnus Själander, Per Larsson-Edefors, Magnus Björk
IEEE Computer Society Annual Symposium on VLSI, p. 15-20
Paper i proceeding
2007

Exposed Datapath for Efficient Computing

Magnus Björk, Magnus Själander, Lars Svensson et al
2007 HiPEAC Workshop on Reconfigurable Computing
Paper i proceeding
2006

Exposed Datapath for Efficient Computing

Magnus Björk, Magnus Själander, Lars Svensson et al
Rapport
2006

Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity

Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran et al
IEEE Intl Symposium on Circuits and Systems (ISCAS)
Paper i proceeding
2006

An Efficient FFT Engine Based on Twin-Precision Computation

Martin Brinck, Kristian Eklund, Magnus Själander et al
Swedish System--on-Chip Conference
Konferensbidrag (offentliggjort, men ej förlagsutgivet)
2005

A Power-Efficient and Versatile Modified-Booth Multiplier

Magnus Själander, Per Larsson-Edefors
Swedish System-on-Chip Conference
Konferensbidrag (offentliggjort, men ej förlagsutgivet)
2005

A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating

Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors et al
IEEE International Symposium on Circuits and Systems, p. 1654-7
Paper i proceeding
2004

An Efficient Twin-Precision Multiplier

Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
International Conference on Computer Design (ICCD), p. 30-33
Paper i proceeding

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