Magnus Själander
Visar 52 publikationer
CREEP: Chalmers RTL-based Energy Evaluation of Pipelines
Data filter cache designs for enhancing energy efficiency and performance in computing systems
Systems and methods for improving processor efficiency through caching
Practical Way Halting by Speculatively Accessing Halt Tags
Redesigning a tagless access buffer to require minimal ISA changes
Improving Data Access Efficiency by Using Context-Aware Loads and Stores
Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)
Towards a Performance- and Energy-Efficient Data Filter Cache
FlexCore: Implementing an Exposed Datapath Processor
Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance
Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches
Viterbi Accelerator for Embedded Processor Datapaths
An LTE Uplink Receiver PHY Benchmark and Subframe-Based Power Management
Configurable RTL Model for Level-1 Caches
Techniques to Measure, Model, and Manage Power
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor
Declarative, SAT-solver-based Scheduling for an Embedded Architecture with a Flexible Datapath
FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation
Infrastructures for Measuring Power
A SAT-Based Compiler for FlexCore
Early results from ERA embedded reconfigurable architectures
Power-Aware Resource Scheduling in Base Stations
Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect
FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation
Multiplication Acceleration through Twin Precision
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements
A Flexible Code-Compression Scheme using Partitioned Look-Up Tables
Scheduling for an Embedded Architecture with a Flexible Datapath
High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture
Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree
Design-Time Scheduling for Processor Exploration
Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture
A Flexible Code Compression Scheme using Partitioned Look-Up Tables
High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree
Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors
Double Throughput MAC for Performance Enhancement of the FlexCore Processor
Efficient and Flexible Embedded Systems and Datapath Components
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures
A Flexible Datapath Interconnect for Embedded Applications
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Exposed Datapath for Efficient Computing
An Efficient FFT Engine Based on Twin-Precision Computation
Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity
Efficient Reconfigurable Multipliers Based on the Twin-Precision Technique
Exposed Datapath for Efficient Computing
A Power-Efficient and Versatile Modified-Booth Multiplier
A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating
An Efficient Twin-Precision Multiplier
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