Magnus Själander
Visar 52 publikationer
Data filter cache designs for enhancing energy efficiency and performance in computing systems
CREEP: Chalmers RTL-based Energy Evaluation of Pipelines
Systems and methods for improving processor efficiency through caching
Practical Way Halting by Speculatively Accessing Halt Tags
Redesigning a tagless access buffer to require minimal ISA changes
Improving Data Access Efficiency by Using Context-Aware Loads and Stores
Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)
Towards a Performance- and Energy-Efficient Data Filter Cache
FlexCore: Implementing an Exposed Datapath Processor
Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance
Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches
An LTE Uplink Receiver PHY Benchmark and Subframe-Based Power Management
Viterbi Accelerator for Embedded Processor Datapaths
Configurable RTL Model for Level-1 Caches
Techniques to Measure, Model, and Manage Power
Declarative, SAT-solver-based Scheduling for an Embedded Architecture with a Flexible Datapath
Reconfigurable Instruction Decoding for a Wide-Control-Word Processor
Infrastructures for Measuring Power
FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation
A SAT-Based Compiler for FlexCore
Early results from ERA embedded reconfigurable architectures
Power-Aware Resource Scheduling in Base Stations
Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect
FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation
Multiplication Acceleration through Twin Precision
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements
A Flexible Code-Compression Scheme using Partitioned Look-Up Tables
High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture
Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture
Scheduling for an Embedded Architecture with a Flexible Datapath
Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree
Design-Time Scheduling for Processor Exploration
High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree
A Flexible Code Compression Scheme using Partitioned Look-Up Tables
Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors
Efficient and Flexible Embedded Systems and Datapath Components
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures
Double Throughput MAC for Performance Enhancement of the FlexCore Processor
A Flexible Datapath Interconnect for Embedded Applications
Exposed Datapath for Efficient Computing
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Efficient Reconfigurable Multipliers Based on the Twin-Precision Technique
Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity
An Efficient FFT Engine Based on Twin-Precision Computation
Exposed Datapath for Efficient Computing
A Power-Efficient and Versatile Modified-Booth Multiplier
A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating
An Efficient Twin-Precision Multiplier
Ladda ner publikationslistor
Du kan ladda ner denna lista till din dator.
Filtrera och ladda ner publikationslista
Som inloggad användare hittar du ytterligare funktioner i MyResearch.
Du kan även exportera direkt till Zotero eller Mendeley genom webbläsarplugins. Dessa hittar du här:
Zotero Connector
Mendeley Web Importer
Tjänsten SwePub erbjuder uttag av Researchs listor i andra format, till exempel kan du få uttag av publikationer enligt Harvard och Oxford i .RIS, BibTex och RefWorks-format.