Viterbi Accelerator for Embedded Processor Datapaths
Paper i proceeding, 2012

We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an embedded processor. We investigate the accelerator’s impact on processor performance by using the EEMBC Viterbi benchmark and the in-house Viterbi Branch Metric kernel. Our evaluation based on the EEMBC benchmark shows that an accelerated 65-nm 2.7-ns processor datapath is 20% larger but 90% more cycle efficient than a datapath lacking the Viterbi accelerator, leading to an 87% overall energy reduction and a data throughput of 3.52 Mbit/s.

hardware/software codesign

embedded processor

energy efficiency

Viterbi decoding

accelerator

Författare

Muhammad Waqar Azhar

Chalmers, Data- och informationsteknik, Datorteknik

Magnus Själander

Chalmers, Data- och informationsteknik, Datorteknik

Ali Hasan

Chalmers, Data- och informationsteknik, Datorteknik

Akshay Vijayashekar

Chalmers, Data- och informationsteknik, Datorteknik

Tung Hoang

Chalmers, Data- och informationsteknik, Datorteknik

Kashan Khurshid Ansari

Chalmers, Data- och informationsteknik

Per Larsson-Edefors

Chalmers, Data- och informationsteknik, Datorteknik

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

10636862 (ISSN)

133-140 6341463

Styrkeområden

Informations- och kommunikationsteknik

Energi

Drivkrafter

Hållbar utveckling

Ämneskategorier

Annan elektroteknik och elektronik

DOI

10.1109/ASAP.2012.24

ISBN

978-076954768-8

Mer information

Skapat

2017-10-07