Towards a Performance- and Energy-Efficient Data Filter Cache
Paper i proceeding, 2013

As CPU data requests to the level-one (L1) data cache (DC) can represent as much as 25% of an embedded processor's total power dissipation, techniques that decrease L1 DC accesses can significantly enhance processor energy efficiency. Filter caches are known to efficiently decrease the number of accesses to instruction caches. However, due to the irregular access pattern of data accesses, a conventional data filter cache (DFC) has a high miss rate, which degrades processor performance. We propose to integrate a DFC with a fast address calculation technique to significantly reduce the impact of misses and to improve performance by enabling one-cycle loads. Furthermore, we show that DFC stalls can be eliminated even after unsuccessful fast address calculations, by simultaneously accessing the DFC and L1 DC on the following cycle. We quantitatively evaluate different DFC configurations, with and without the fast address calculation technique, using different write allocation policies, and qualitatively describe their impact on energy efficiency. The proposed design provides an efficient DFC that yields both energy and performance improvements.

Data cache

Execution time

Speculation

Energy

Memory hierarchy

Författare

Alen Bardizbanyan

Chalmers, Data- och informationsteknik, Datorteknik

Magnus Själander

Chalmers, Data- och informationsteknik, Datorteknik

David Whalley

Florida State University

Per Larsson-Edefors

Chalmers, Data- och informationsteknik, Datorteknik

Workshop on Optimizations for DSP and Embedded Systems (ODES), Proceedings of International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27,

21-28

Styrkeområden

Informations- och kommunikationsteknik

Energi

Drivkrafter

Hållbar utveckling

Ämneskategorier

Datorsystem

DOI

10.1145/2443608.2443614

ISBN

978-145031905-8

Mer information

Skapat

2017-10-07